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| Order this document by UC3844B/D UC3844B, 45B UC2844B, 45B High Performance Current Mode Controllers The UC3844B, UC3845B series are high performance fixed frequency current mode controllers. They are specifically designed for Off-Line and dc-to-dc converter applications offering the designer a cost-effective solution with minimal external components. These integrated circuits feature an oscillator, a temperature compensated reference, high gain error amplifier, current sensing comparator, and a high current totem pole output ideally suited for driving a power MOSFET. Also included are protective features consisting of input and reference undervoltage lockouts each with hysteresis, cycle-by-cycle current limiting, a latch for single pulse metering, and a flip-flop which blanks the output off every other oscillator cycle, allowing output deadtimes to be programmed from 50% to 70%. These devices are available in an 8-pin dual-in-line and surface mount (SO-8) plastic package as well as the 14-pin plastic surface mount (SO-14). The SO-14 package has separate power and ground pins for the totem pole output stage. The UCX844B has UVLO thresholds of 16 V (on) and 10 V (off), ideally suited for off-line converters. The UCX845B is tailored for lower voltage applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off). * Trimmed Oscillator for Precise Frequency Control HIGH PERFORMANCE CURRENT MODE CONTROLLERS N SUFFIX PLASTIC PACKAGE CASE 626 8 1 D1 SUFFIX PLASTIC PACKAGE CASE 751 (SO-8) D SUFFIX PLASTIC PACKAGE CASE 751A (SO-14) 8 1 14 1 * * * * * * * * * Oscillator Frequency Guaranteed at 250 kHz Current Mode Operation to 500 kHz Output Switching Frequency Output Deadtime Adjustable from 50% to 70% Automatic Feed Forward Compensation Latching PWM for Cycle-By-Cycle Current Limiting Internally Trimmed Reference with Undervoltage Lockout High Current Totem Pole Output Undervoltage Lockout with Hysteresis Low Startup and Operating Current Compensation 1 NC 2 Voltage Feedback 3 NC 4 Current Sense 5 NC 6 RT/CT 7 VCC 7(12) PIN CONNECTIONS Compensation 1 Voltage Feedback 2 Current Sense 3 RT/CT 4 (Top View) 14 V ref 13 NC 12 VCC 11 8 7 6 5 Vref VCC Output Gnd VC Gnd Power Ground 10 Output 9 8 Simplified Block Diagram (Top View) Vref 8(14) R R Vref Undervoltage Lockout 5.0V Reference VCC Undervoltage Lockout ORDERING INFORMATION Device VC 7(11) Output 6(10) Power Ground 5(8) Operating Temperature Range Package SO-14 UC384XBD UC384XBD1 UC384XBN UC284XBD UC284XBD1 UC284XBN UC384XBVD UC384XBVD1 TA = - 40 to +105C UC384XBVN X indicates either a 4 or 5 to define specific device part numbers. (c) Motorola, Inc. 1996 TA = 0 to + 70C SO-8 Plastic SO-14 RT/CT 4(7) Voltage Feedback Input Output/ Compensation 1(1) Oscillator Latching PWM TA = - 25 to + 85C SO-8 Plastic SO-14 SO-8 Plastic 2(3) Error Amplifier 3(5) Gnd 5(9) Current Sense Input Pin numbers in parenthesis are for the D suffix SO-14 package. Rev 1 MOTOROLA ANALOG IC DEVICE DATA 1 UC3844B, 45B UC2844B, 45B MAXIMUM RATINGS Rating Total Power Supply and Zener Current Output Current, Source or Sink (Note 1) Output Energy (Capacitive Load per Cycle) Current Sense and Voltage Feedback Inputs Error Amp Output Sink Current Power Dissipation and Thermal Characteristics D Suffix, Plastic Package, SO-14 Case 751A Maximum Power Dissipation @ TA = 25C Thermal Resistance, Junction-to-Air D1 Suffix, Plastic Package, SO-8 Case 751 Maximum Power Dissipation @ TA = 25C Thermal Resistance, Junction-to-Air N Suffix, Plastic Package, Case 626 Maximum Power Dissipation @ TA = 25C Thermal Resistance, Junction-to-Air Operating Junction Temperature Operating Ambient Temperature UC3844B, UC3845B UC2844B, UC2845B Storage Temperature Range Symbol (ICC + IZ) IO W Vin IO Value 30 1.0 5.0 - 0.3 to + 5.5 10 Unit mA A J V mA PD RJA PD RJA PD RJA TJ TA 862 145 702 178 1.25 100 +150 0 to + 70 - 25 to + 85 mW C/W mW C/W W C/W C C Tstg - 65 to +150 C ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF. For typical values TA = 25C, for min/max values TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.) UC284XB Characteristic REFERENCE SECTION Reference Output Voltage (IO = 1.0 mA, TJ = 25C) Line Regulation (VCC = 12 V to 25 V) Load Regulation (IO = 1.0 mA to 20 mA) Temperature Stability Total Output Variation over Line, Load, and Temperature Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25C) Long Term Stability (TA = 125C for 1000 Hours) Output Short Circuit Current OSCILLATOR SECTION Frequency TJ = 25C TA = Tlow to Thigh TJ = 25C (RT = 6.2 k, CT = 1.0 nF) Frequency Change with Voltage (VCC = 12 V to 25 V) Frequency Change with Temperature TA = Tlow to Thigh Oscillator Voltage Swing (Peak-to-Peak) Discharge Current (VOSC = 2.0 V) TJ = 25C TA = Tlow to Thigh (UC284XB, UC384XB) TA = Tlow to Thigh (UC384XBV) fOSC 49 48 225 fOSC/V fOSC/T VOSC Idischg 7.8 7.5 - 8.3 - - 8.8 8.8 - 7.8 7.6 7.2 8.3 - - 8.8 8.8 8.8 - - - 52 - 250 0.2 1.0 1.6 55 56 275 1.0 - - 49 48 225 - - - 52 - 250 0.2 0.5 1.6 55 56 275 1.0 - - % % V mA kHz Vref Regline Regload TS Vref Vn S ISC 4.95 - - - 4.9 - - - 30 5.0 2.0 3.0 0.2 - 50 5.0 - 85 5.05 20 25 - 5.1 - - -180 4.9 - - - 4.82 - - - 30 5.0 2.0 3.0 0.2 - 50 5.0 - 85 5.1 20 25 - 5.18 - - -180 V mV mV mV/C V V mV mA Symbol Min Typ Max UC384XB, XBV Min Typ Max Unit NOTES: 1. Maximum package power dissipation limits must be observed. 2. Adjust VCC above the Startup threshold before setting to 15 V. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0C for UC3844B, UC3845B Thigh = + 70C for UC3844B, UC3845B = - 25C for UC2844B, UC2845B = + 85C for UC2844B, UC2845B = - 40C for UC3844BV, UC3845BV = +105C for UC3844BV, UC3845BV 2 MOTOROLA ANALOG IC DEVICE DATA UC3844B, 45B UC2844B, 45B ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF. For typical values TA = 25C, for min/max values TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.) UC284XB Characteristic ERROR AMPLIFIER SECTION Voltage Feedback Input (VO = 2.5 V) Input Bias Current (VFB = 5.0 V) Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) Unity Gain Bandwidth (TJ = 25C) Power Supply Rejection Ratio (VCC = 12 V to 25 V) Output Current Sink (VO = 1.1 V, VFB = 2.7 V) Source (VO = 5.0 V, VFB = 2.3 V) Output Voltage Swing High State (RL = 15 k to ground, VFB = 2.3 V) Low State (RL = 15 k to Vref, VFB = 2.7 V) (UC284XB, UC384XB) (UC384XBV) CURRENT SENSE SECTION Current Sense Input Voltage Gain (Notes 4 & 5) (UC284XB, UC384XB) (UC384XBV) Maximum Current Sense Input Threshold (Note 4) (UC284XB, UC384XB) (UC384XBV) Power Supply Rejection Ratio (VCC = 12 V to 25 V) (Note 4) Input Bias Current Propagation Delay (Current Sense Input to Output) OUTPUT SECTION Output Voltage Low State (ISink = 20 mA) (ISink = 200 mA, UC284XB, UC384XB) (ISink = 200 mA, UC384XBV) High State (ISource = 20 mA, UC284XB, UC384XB) (ISource = 20 mA, UC384XBV) (ISource = 200 mA) Output Voltage with UVLO Activated VCC = 6.0 V, ISink = 1.0 mA Output Voltage Rise Time (CL = 1.0 nF, TJ = 25C) Output Voltage Fall Time (CL = 1.0 nF, TJ = 25C) UNDERVOLTAGE LOCKOUT SECTION Startup Threshold UCX844B, BV UCX845B, BV Minimum Operating Voltage After Turn-On UCX844B, BV UCX845B, BV Vth 15 7.8 VCC(min) 9.0 7.0 10 7.6 11 8.2 8.5 7.0 10 7.6 11.5 8.2 16 8.4 17 9.0 14.5 7.8 16 8.4 17.5 9.0 V V V VOL - - - 13 - 12 - - - 0.1 1.6 - 13.5 - 13.4 0.1 50 50 0.4 2.2 - - - - 1.1 150 150 - - - 13 12.9 12 - - - 0.1 1.6 1.6 13.5 - 13.4 0.1 50 50 0.4 2.2 2.3 - - - 1.1 150 150 V ns ns AV 2.85 - Vth 0.9 - PSRR IIB tPLH(In/Out) - - - 1.0 - 70 - 2.0 150 1.1 - - -10 300 0.9 0.85 - - - 1.0 1.0 70 - 2.0 150 1.1 1.1 - -10 300 dB A ns 3.0 - 3.15 - 2.85 2.85 3.0 3.0 3.15 3.25 V V/V VFB IIB AVOL BW PSRR ISink ISource VOH VOL 2.45 - 65 0.7 60 2.0 - 0.5 5.0 - - 2.5 - 0.1 90 1.0 70 12 -1.0 6.2 0.8 - 2.55 -1.0 - - - - - - 1.1 - 2.42 - 65 0.7 60 2.0 - 0.5 5.0 - - 2.5 - 0.1 90 1.0 70 12 -1.0 6.2 0.8 0.8 2.58 - 2.0 - - - - - V - 1.1 1.2 V A dB MHz dB mA Symbol Min Typ Max UC384XB, XBV Min Typ Max Unit VOH VOL(UVLO) tr tf NOTES: 2. Adjust VCC above the Startup threshold before setting to 15 V. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0C for UC3844B, UC3845B Thigh = + 70C for UC3844B, UC3845B Tlow = - 25C for UC2844B, UC2845B T high = + 85C for UC2844B, UC2845B Tlow = - 40C for UC3844BV, UC3845BV Th igh = +105C for UC3844BV, UC3845BV 4. This parameter is measured at the latch trip point with VFB = 0 V. DV Output Compensation 5. Comparator gain is defined as: AV = DV Current Sense Input MOTOROLA ANALOG IC DEVICE DATA 3 UC3844B, 45B UC2844B, 45B ELECTRICAL CHARACTERISTICS (VCC = 15 V [Note 2], RT = 10 k, CT = 3.3 nF. For typical values TA = 25C, for min/max values TA is the operating ambient temperature range that applies [Note 3], unless otherwise noted.) UC284XB Characteristic PWM SECTION Duty Cycle Maximum (UC284XB, UC384XB) Maximum (UC384XBV) Minimum TOTAL DEVICE Power Supply Current Startup (VCC = 6.5 V for UCX845B, Start-Up (VCC 14 V for UCX844B, BV) Operating (Note 2) Power Supply Zener Voltage (ICC = 25 mA) ICC - - VZ 30 0.3 12 36 0.5 17 - - - 30 0.3 12 36 0.5 17 - V mA % DC(max) DC(min) 47 - - 48 - - 50 - 0 47 46 - 48 48 - 50 50 0 Symbol Min Typ Max UC384XB, XBV Min Typ Max Unit NOTES: 2. Adjust VCC above the Startup threshold before setting to 15 V. 3. Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible. Tlow = 0C for UC3844B, UC3845B Thigh = + 70C for UC3844B, UC3845B = - 25C for UC2844B, UC2845B = + 85C for UC2844B, UC2845B = - 40C for UC3844BV, UC3845BV = +105C for UC3844BV, UC3845BV Figure 1. Timing Resistor versus Oscillator Frequency 80 50 R T, TIMING RESISTOR (k ) 20 8.0 5.0 2.0 0.8 10 k NOTE: Output switches at 1/2 the oscillator frequency 20 k 50 k 100 k 200 k 500 k fOSC, OSCILLATOR FREQUENCY (kHz) 1.0 M % DT, PERCENT OUTPUT DEADTIME VCC = 15 V TA = 25C 75 70 65 60 55 1. 2. 3. 4. 5. 6. 7. Figure 2. Output Deadtime versus Oscillator Frequency 50 10 k Figure 3. Error Amp Small Signal Transient Response 2.55 V VCC = 15 V AV = -1.0 TA = 25C 3.0 V 20 mV/DIV 2.5 V 2.5 V 2.45 V 0.5 s/DIV 2.0 V 1.0 s/DIV 4 MOTOROLA ANALOG IC DEVICE DATA 200 mV/DIV AAAA AAAA AAAA AAAA AAAA CT = 10 nF CT = 5.0 nF CT = 2.0 nF CT = 1.0 nF CT = 500 pF CT = 200 pF CT = 100 pF 20 k 3 2 1 4 7 5 6 50 k 100 k 200 k 500 k fOSC, OSCILLATOR FREQUENCY (kHz) 1.0 M Figure 4. Error Amp Large Signal Transient Response VCC = 15 V AV = -1.0 TA = 25C UC3844B, 45B UC2844B, 45B Figure 5. Error Amp Open Loop Gain and Phase versus Frequency A VOL , OPEN LOOP VOLTAGE GAIN (dB) 100 80 Gain 60 40 Phase 20 0 - 20 10 VCC = 15 V VO = 2.0 V to 4.0 V RL = 100 k TA = 25C 0 , EXCESS PHASE (DEGREES) 30 60 90 Vth , CURRENT SENSE INPUT THRESHOLD (V) Figure 6. Current Sense Input Threshold versus Error Amp Output Voltage 1.2 VCC = 15 V 1.0 0.8 TA = 25C 0.6 TA = 125C 0.4 TA = - 55C 0.2 0 120 150 180 10 M 100 1.0 k 10 k 100 k f, FREQUENCY (Hz) 1.0 M 0 2.0 4.0 6.0 VO, ERROR AMP OUTPUT VOLTAGE (VO) 8.0 ISC , REFERENCE SHORT CIRCUIT CURRENT (mA) Vref , REFERENCE VOLTAGE CHANGE (mV) Figure 7. Reference Voltage Change versus Source Current 0 VCC = 15 V - 4.0 - 8.0 - 12 TA = 125C - 16 - 20 TA = 25C - 24 0 20 40 60 80 100 Iref, REFERENCE SOURCE CURRENT (mA) 120 TA = - 55C Figure 8. Reference Short Circuit Current versus Temperature 90 70 50 - 55 - 25 0 25 50 75 TA, AMBIENT TEMPERATURE (C) V , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV) VCC = 15 V IO = 1.0 mA to 20 mA TA = 25C V , OUTPUT VOLTAGE CHANGE (2.0 mV/DIV) Figure 9. Reference Load Regulation Figure 10. Reference Line Regulation VCC = 12 V to 25 V TA = 25C 2.0 ms/DIV 2.0 ms/DIV MOTOROLA ANALOG IC DEVICE DATA AAAA AAAA VCC = 15 V RL 0.1 100 125 110 O O 5 UC3844B, 45B UC2844B, 45B Figure 11. Output Saturation Voltage versus Load Current Vsat , OUTPUT SATURATION VOLTAGE (V) -1.0 - 2.0 Figure 12. Output Waveform VCC = 15 V CL = 1.0 nF TA = 25C 3.0 2.0 1.0 0 0 V O , OUTPUT VOLTAGE ICC, SUPPLY CURRENT (mA) 20 V/DIV ICC, SUPPLY CURRENT UCX845B UCX844B 5 0 0 10 100 ns/DIV 20 30 VCC, SUPPLY VOLTAGE (V) PIN FUNCTION DESCRIPTION Pin 8-Pin 1 2 3 4 5 6 7 8 10 12 14 8 11 9 2,4,6,13 14-Pin 1 3 5 7 Function F i Compensation Voltage Feedback Current Sense RT/CT Gnd Output VCC Vref Power Ground VC Gnd NC Description D ii This pin is the Error Amplifier output and is made available for loop compensation. This is the inverting input of the Error Amplifier. It is normally connected to the switching power supply output through a resistor divider. A voltage proportional to inductor current is connected to this input. The PWM uses this information to terminate the output switch conduction. The Oscillator frequency and maximum Output duty cycle are programmed by connecting resistor RT to Vref and capacitor CT to ground. Oscillator operation to 1.0 kHz is possible. This pin is the combined control circuitry and power ground. This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced and sunk by this pin. The output switches at one-half the oscillator frequency. This pin is the positive supply of the control IC. This is the reference output. It provides charging current for capacitor CT through resistor RT. This pin is a separate power ground return that is connected back to the power source. It is used to reduce the effects of switching transient noise on the control circuitry. The Output high state (VOH) is set by the voltage applied to this pin. With a separate power source connection, it can reduce the effects of switching transient noise on the control circuitry. This pin is the control circuitry ground return and is connected back to the power source ground. No connection. These pins are not internally connected. 6 MOTOROLA ANALOG IC DEVICE DATA AAAA AAAA AAAA 100 mA/DIV AAAAAAA A AAAAAAAAAAAA AAA A AAAAAAAAA AAAAAAAAA AA AAAAAAAAAAAAA AAAAA AA VCC TA = 25C Source Saturation (Load to Ground) VCC = 15 V 80 s Pulsed Load 120 Hz Rate TA = - 55C TA = - 55C TA = 25C Sink Saturation (Load to VCC) Gnd 200 400 600 I O, OUTPUT LOAD CURRENT (mA) 0 90% 10% 800 50 ns/DIV Figure 13. Output Cross Conduction VCC = 30 V CL = 15 pF TA = 25C Figure 14. Supply Current versus Supply Voltage 25 20 15 10 RT = 10 k CT = 3.3 nF VFB = 0 V ISense = 0 V TA = 25C 40 UC3844B, 45B UC2844B, 45B OPERATING DESCRIPTION The UC3844B, UC3845B series are high performance, fixed frequency, current mode controllers. They are specifically designed for Off-Line and dc-to-dc converter applications offering the designer a cost-effective solution with minimal external components. A representative block diagram is shown in Figure 15. Oscillator The oscillator frequency is programmed by the values selected for the timing components RT and CT. Capacitor CT is charged from the 5.0 V reference through resistor RT to approximately 2.8 V and discharged to 1.2 V by an internal current sink. During the discharge of CT, the oscillator generates an internal blanking pulse that holds the center input of the NOR gate high. This causes the Output to be in a low state, thus producing a controlled amount of output deadtime. An internal flip-flop has been incorporated in the UCX844/5B which blanks the output off every other clock cycle by holding one of the inputs of the NOR gate high. This in combination with the CT discharge period yields output deadtimes programmable from 50% to 70%. Figure 1 shows RT versus Oscillator Frequency and Figure 2, Output Deadtime versus Frequency, both for given values of CT. Note that many values of RT and CT will give the same oscillator frequency but only one combination will yield a specific output deadtime at a given frequency. The oscillator thresholds are temperature compensated to within 6% at 50 kHz. Also, because of industry trends moving the UC384X into higher and higher frequency applications, the UC384XB is guaranteed to within 10% at 250 kHz. In many noise-sensitive applications it may be desirable to frequency-lock the converter to an external system clock. This can be accomplished by applying a clock signal to the circuit shown in Figure 17. For reliable locking, the free-running oscillator frequency should be set about 10% less than the clock frequency. A method for multi-unit synchronization is shown in Figure 18. By tailoring the clock waveform, accurate Output duty cycle clamping can be achieved to realize output deadtimes of greater than 70%. Error Amplifier A fully compensated Error Amplifier with access to the inverting input and output is provided. It features a typical dc voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz with 57 degrees of phase margin (Figure 5). The non-inverting input is internally biased at 2.5 V and is not pinned out. The converter output voltage is typically divided down and monitored by the inverting input. The maximum input bias current is -2.0 A which can cause an output voltage error that is equal to the product of the input bias current and the equivalent input divider source resistance. The Error Amp Output (Pin 1) is provided for external loop compensation (Figure 28). The output voltage is offset by two diode drops (1.4 V) and divided by three before it connects to the inverting input of the Current Sense Comparator. This guarantees that no drive pulses appear at the Output (Pin 6) when Pin 1 is at its lowest state (VOL). This occurs when the power supply is operating and the load is removed, or at the beginning of a soft-start interval (Figures 20, 21). The Error Amp minimum feedback resistance is limited by the amplifier's source current (0.5 mA) and the required output voltage (VOH) to reach the comparator's 1.0 V clamp level: Rf(min) 3.0 (1.0 V) + 1.4 V 0.5 mA = 8800 Current Sense Comparator and PWM Latch The UC3844B, UC3845B operate as a current mode controller, whereby output switch conduction is initiated by the oscillator and terminated when the peak inductor current reaches the threshold level established by the Error Amplifier Output/Compensation (Pin 1). Thus the error signal controls the peak inductor current on a cycle-by-cycle basis. The Current Sense Comparator PWM Latch configuration used ensures that only a single pulse appears at the Output during any given oscillator cycle. The inductor current is converted to a voltage by inserting the ground-referenced sense resistor RS in series with the source of output switch Q1. This voltage is monitored by the Current Sense Input (Pin 3) and compared to a level derived from the Error Amp Output. The peak inductor current under normal operating conditions is controlled by the voltage at Pin 1 where: Ipk = V(Pin 1) - 1.4 V 3 RS Abnormal operating conditions occur when the power supply output is overloaded or if output voltage sensing is lost. Under these conditions, the Current Sense Comparator threshold will be internally clamped to 1.0 V. Therefore the maximum peak switch current is: Ipk(max) = 1.0 V RS When designing a high power switching regulator it becomes desirable to reduce the internal clamp voltage in order to keep the power dissipation of RS to a reasonable level. A simple method to adjust this voltage is shown in Figure 19. The two external diodes are used to compensate the internal diodes, yielding a constant clamp voltage over temperature. Erratic operation due to noise pickup can result if there is an excessive reduction of the Ipk(max) clamp voltage. A narrow spike on the leading edge of the current waveform can usually be observed and may cause the power supply to exhibit an instability when the output is lightly loaded. This spike is due to the power transformer interwinding capacitance and output rectifier recovery time. The addition of an RC filter on the Current Sense Input with a time constant that approximates the spike duration will usually eliminate the instability (refer to Figure 23). MOTOROLA ANALOG IC DEVICE DATA 7 UC3844B, 45B UC2844B, 45B Figure 15. Representative Block Diagram VCC Vin VCC 7(12) 36V Vref 8(14) RT 2.5V R R Internal Bias 3.6V Oscillator CT 4(7) + 1.0mA Reference Regulator VCC UVLO + - Vref UVLO + - (See Text) VC 7(11) Output 6(10) Q1 S Voltage Feedback Input 2(3) Output/ Compensation 1(1) 2R R Error Amplifier R 1.0V Current Sense Comparator Gnd 5(9) Q PWM Latch Power Ground 5(8) Current Sense Input 3(5) RS Pin numbers adjacent to terminals are for the 8-pin dual-in-line package. Pin numbers in parenthesis are for the D suffix SO-14 package. = Sink Only Positive True Logic Figure 16. Timing Diagram Capacitor CT Latch "Set" Input Output/ Compensation Current Sense Input Latch "Reset" Input Output Large RT/Small CT Small RT/Large CT 8 MOTOROLA ANALOG IC DEVICE DATA UC3844B, 45B UC2844B, 45B Undervoltage Lockout Two undervoltage lockout comparators have been incorporated to guarantee that the IC is fully functional before the output stage is enabled. The positive power supply terminal (VCC) and the reference output (Vref) are each monitored by separate comparators. Each has built-in hysteresis to prevent erratic output behavior as their respective thresholds are crossed. The VCC comparator upper and lower thresholds are 16 V/10 V for the UCX844B, and 8.4 V/7.6 V for the UCX845B. The Vref comparator upper and lower thresholds are 3.6 V/3.4 V. The large hysteresis and low startup current of the UCX844B makes it ideally suited in off-line converter applications where efficient bootstrap startup techniques are required (Figure 29). The UCX845B is intended for lower voltage dc-to-dc converter applications. A 36 V zener is connected as a shunt regulator from VCC to ground. Its purpose is to protect the IC from excessive voltage that can occur during system startup. The minimum operating voltage for the UCX844B is 11 V and 8.2 V for the UCX845B. Output These devices contain a single totem pole output stage that was specifically designed for direct drive of power MOSFETs. It is capable of up to 1.0 A peak drive current and has a typical rise and fall time of 50 ns with a 1.0 nF load. Additional internal circuitry has been added to keep the Output in a sinking mode whenever an undervoltage lockout is active. This characteristic eliminates the need for an external pull-down resistor. The SO-14 surface mount package provides separate pins for VC (output supply) and Power Ground. Proper implementation will significantly reduce the level of switching transient noise imposed on the control circuitry. This becomes particularly useful when reducing the Ipk(max) clamp level. The separate VC supply input allows the designer added flexibility in tailoring the drive voltage independent of VCC. A zener clamp is typically connected to this input when driving power MOSFETs in systems where VCC is greater than 20 V. Figure 22 shows proper power and control ground connections in a current-sensing power MOSFET application. Reference The 5.0 V bandgap reference is trimmed to 1.0% tolerance at TJ = 25C on the UC284XB, and 2.0% on the UC384XB. Its primary purpose is to supply charging current to the oscillator timing capacitor. The reference has short-circuit protection and is capable of providing in excess of 20 mA for powering additional control system circuitry. Design Considerations Do not attempt to construct the converter on wire-wrap or plug-in prototype boards. High frequency circuit layout techniques are imperative to prevent pulse-width jitter. This is usually caused by excessive noise pick-up imposed on the Current Sense or Voltage Feedback inputs. Noise immunity can be improved by lowering circuit impedances at these points. The printed circuit layout should contain a ground plane with low-current signal and high-current switch and output grounds returning on separate paths back to the input filter capacitor. Ceramic bypass capacitors (0.1 F) connected directly to VCC, VC, and Vref may be required depending upon circuit layout. This provides a low impedance path for filtering the high frequency noise. All high current loops should be kept as short as possible using heavy copper runs to minimize radiated EMI. The Error Amp compensation circuitry and the converter output voltage divider should be located close to the IC and as far as possible from the power switch and other noise-generating components. Figure 17. External Clock Synchronization Figure 18. External Duty Cycle Clamp and Multi-Unit Synchronization Vref 8(14) RT R Bias R RB 6 Osc CT 0.01 External Sync Input EA 4(7) + 2R 47 2(3) R C R 5 2 5.0k 1 1(1) 5(9) 1(1) To Additional UCX84XBs 5(9) 5.0k S Q 7 2(3) EA 4(7) + 2R R RA 8 5.0k 4 3 Osc R 8(14) R Bias MC1455 The diode clamp is required if the Sync amplitude is large enough to cause the bottom side of CT to go more than 300 mV below ground. f 1.44 + (RA ) 2RB)C D(max) R + RA )A 2RB MOTOROLA ANALOG IC DEVICE DATA 9 UC3844B, 45B UC2844B, 45B Figure 19. Adjustable Reduction of Clamp Level VCC 7(12) 5.0V Ref 5.0V Ref 8(14) R Bias R + - Osc 4(7) R2 EA + 1.0 mA 2(3) 2R R 1.0V 1(1) R1 5(9) VClamp S Q R Comp/Latch 1(1) 3(5) RS C 5(8) 1.0M T 6(10) 2(3) EA 2R R 1.0V R + - 7(11) Q1 Osc 4(7) + 1.0mA S Q T 8(14) R Bias R + - Vin Figure 20. Soft-Start Circuit tSoft-Start 3600C in F R1R2 R1 R2 5(9) VClamp 1.67 + 0.33x10-3 R2 1 R1 ) ) Where: 0 VClamp 1.0 V Ipk(max) [ VClamp RS Figure 21. Adjustable Buffered Reduction of Clamp Level with Soft-Start VCC 7(12) Vin Figure 22. Current Sensing Power MOSFET VCC (12) Vin VPin 5 S Ipk [ rRDM(on) rDS(on) ) RS If: SENSEFET = MTP10N10M RS = 200 5.0V Ref 8(14) R Bias R + - Osc 4(7) + 1.0 mA 2(3) R2 1(1) C R1 MPSA63 5(9) EA 2R R 1.0V VClamp T S Q R Comp/Latch 3(5) RS Control Circuitry Ground: To Pin (9) 5(8) 6(10) S Q R Comp/Latch (5) RS 1/4 W Power Ground: To Input Source Return (8) + - 7(11) Q1 T (10) + - 5.0V Ref + - (11) G K M Then : VPin 5 D SENSEFET S [ 0.075 Ipk VClamp 1.67 R2 1 R1 ) Where: 0 VClamp 1.0 V tSoft-Start VC + * In 1 * 3VClamp C R 1 R2 R1 R2 ) Ipk(max) [ VClamp RS Virtually lossless current sensing can be achieved with the implementation of a SENSEFET power switch. For proper operation during over-current conditions, a reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 19 and 21. 10 MOTOROLA ANALOG IC DEVICE DATA UC3844B, 45B UC2844B, 45B Figure 23. Current Waveform Spike Suppression VCC 7(12) Vin 5.0V Ref + - + - T S Q R Comp/Latch 3(5) C R RS 6(10) 5(8) 7(11) Q1 The addition of the RC filter will eliminate instability caused by the leading edge spike on the current waveform. Figure 24. MOSFET Parasitic Oscillations VCC 7(12) Vin + 0 5.0V Ref + - + - 7(11) Rg T S Q R Comp/Latch 3(5) RS 5(8) 6(10) Q1 - Figure 25. Bipolar Transistor Drive IB Vin Base Charge Removal C1 Q1 6(10) 5(8) 3(5) RS Series gate resistor Rg will damp any high frequency parasitic oscillations caused by the MOSFET input capacitance and any series wiring inductance in the gate-source circuit. The totem pole output can furnish negative base current for enhanced transistor turn-off, with the addition of capacitor C1. MOTOROLA ANALOG IC DEVICE DATA 11 UC3844B, 45B UC2844B, 45B Figure 26. Isolated MOSFET Drive VCC 7(12) Isolation Boundary 5.0V Ref + - + - T S Q R Comp/Latch 3(5) C R RS NS 7(11) Q1 + 0 - 6(10) 5(8) 50% DC VGS Waveforms + 0 - 25% DC Vin Ipk = V(Pin 1) - 1.4 3 RS NS Np NP Figure 27. Latched Shutdown 8(14) R Bias R Osc 4(7) + 1.0 mA 2(3) 2R R EA 1(1) MCR 101 2N 3905 2N 3903 5(9) The MCR101 SCR must be selected for a holding of < 0.5 mA @ TA(min). The simple two transistor circuit can be used in place of the SCR as shown. All resistors are 10 k. Figure 28. Error Amplifier Compensation From VO Ri Rd Cf 2.5V + 1.0mA 2(3) Rf 1(1) Rf 8.8k 5(9) EA 2R R From VO Rp Cp 2.5V + 2(3) Rd Cf Rf 1(1) 5(9) EA 1.0mA 2R R Ri Error Amp compensation circuit for stabilizing any current mode topology except for boost and flyback converters operating with continuous inductor current. Error Amp compensation circuit for stabilizing current mode boost and flyback topologies operating with continuous inductor current. 12 MOTOROLA ANALOG IC DEVICE DATA UC3844B, 45B UC2844B, 45B Figure 29. 7 W Off-Line Flyback Regulator L1 MBR1635 4.7 MDA 202 + 250 56k 1N4935 7(12) + 68 100 5.0V Ref 0.01 8(14) 33k R Osc 1.0nF 18k 100 pF 4(7) 2(3) R 4.7k 150k 1(1) 5(9) EA Comp/Latch 3(5) 470pF R Bias 1N4937 4.7k 3300 pF T1 2200 MUR110 1N4935 + 47 1000 MUR110 7(11) 22 T S Q 5(8) 1.0k 0.5 6(10) 1N5819 MTP 4N50 680pF 2.7k 1000 + 1000 + 5.0V/4.0A 115 Vac 5.0V RTN + L2 10 + 12V/0.3A 12V RTN + - + - + + 10 L3 + -12V/0.3A 1N4937 T1 - Primary: 45 Turns #26 AWG Secondary 12 V: 9 Turns #30 AWG (2 Strands) Bifiliar Wound Secondary 5.0 V: 4 Turns (six strands) #26 Hexfiliar Wound Secondary Feedback: 10 Turns #30 AWG (2 strands) Bifiliar Wound Core: Ferroxcube EC35-3C8 Bobbin: Ferroxcube EC35PCB1 Gap: 0.10" for a primary inductance of 1.0 mH L1 - 15 H at 5.0 A, Coilcraft Z7156 L2, L3 - 25 H at 5.0 A, Coilcraft Z7157 Test Line Regulation: 5.0 V 12 V Conditions Vin = 95 Vac to 130 Vac Vin = 115 Vac, Iout = 1.0 A to 4.0 A Vin = 115 Vac, Iout = 100 mA to 300 mA Vin = 115 Vac Vin = 115 Vac Results = 50 mV or 0.5% = 24 mV or 0.1% = 300 mV or 3.0% = 60 mV or 0.25% 40 mVpp 80 mVpp 70% Load Regulation: 5.0 V 12 V Output Ripple: Efficiency 5.0 V 12 V All outputs are at nominal load currents unless otherwise noted. MOTOROLA ANALOG IC DEVICE DATA 13 UC3844B, 45B UC2844B, 45B Figure 30. Step-Up Charge Pump Converter Vin = 15V UC3845B 7(12) 34V 8(14) 10k Reference Regulator 2.5V R R Internal Bias 3.6V Osc 1.0nF 4(7) 2(3) Error Amplifier 1(1) 5(9) VCC + UVLO - Output Load Regulation (Open Loop Configuration) + IO (mA) 47 VO (V) 29.9 28.8 28.3 27.4 24.4 7(11) 1N5819 0 2 9 18 36 1N5819 + - Vref UVLO T 6(10) 15 10 + 0.5mA 2R R 1.0V S R + 5(8) PWM Latch Connect to Pin 2 for closed loop operation. R2 VO 2 (Vin) + 47 Q 3(5) R1 Current Sense Comparator VO = 2.5 R2 R1 )1 The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. The converter's output can provide excellent line and load regulation by connecting the R2/R1 resistor divider as shown. Figure 31. Voltage-Inverting Charge Pump Converter Vin = 15V UC3845B 7(12) 34V 8(14) 10k Reference Regulator 2.5V R R Internal Bias 3.6V Osc 1.0nF 4(7) 2(3) Error Amplifier 1(1) 5(9) VCC + UVLO - Output Load Regulation + IO (mA) 0 2 9 18 32 1N5819 VO -Vin 1N5819 47 VO (V) -14.4 -13.2 -12.5 -11.7 -10.6 7(11) + - Vref UVLO T 6(10) 15 10 + 0.5mA 2R R 1.0V S R + 5(8) Q PWM Latch 3(5) 47 Current Sense Comparator The capacitor's equivalent series resistance must limit the Drive Output current to 1.0 A. An additional series resistor may be required when using tantalum or other low ESR capacitors. OUTLINE DIMENSIONS 14 MOTOROLA ANALOG IC DEVICE DATA UC3844B, 45B UC2844B, 45B N SUFFIX PLASTIC PACKAGE CASE 626-05 ISSUE K 8 5 -B- 1 4 NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040 F NOTE 2 -A- L C -T- SEATING PLANE J N D K M M H G 0.13 (0.005) TA M B M D1 SUFFIX PLASTIC PACKAGE CASE 751-05 (SO-8) ISSUE N -A- 8 5 -B- 1 4 4X P 0.25 (0.010) M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.18 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.189 0.196 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.007 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 G C -T- 8X SEATING PLANE R X 45 _ F D 0.25 (0.010) M K TB M_ S J S A MOTOROLA ANALOG IC DEVICE DATA 15 UC3844B, 45B UC2844B, 45B OUTLINE DIMENSIONS D SUFFIX PLASTIC PACKAGE CASE 751A-03 (SO-14) ISSUE F 8 -A- 14 -B- 1 7 P 7 PL 0.25 (0.010) M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. G C R X 45 _ F -T- SEATING PLANE D 14 PL 0.25 (0.010) M K TB S M A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 or 602-303-5454 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 INTERNET: http://Design-NET.com JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-81-3521-8315 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 16 MOTOROLA ANALOG IC DEVICE DATA *UC3844B/D* UC3844B/D |
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